1. Field of the Invention
The present invention is directed in general to the field of data processing systems. In one aspect, the present invention relates to cache memory management within multiprocessor systems.
2. Description of the Related Art
In multi-processor computer systems having one or more levels of cache memory at each processor, cache coherency is typically maintained across such systems using a snoop protocol or a directory-based protocol. Where a snoop protocol is used to provide system coherency for cache lines with existing multi-processor systems, there is a large amount of sharing of cache lines, upwards of 30% of all requests in some cases. This may be understood with reference to a multi-core system, such as the POWER5/6 which uses a snoop protocol to maintain coherency. In such a system, lines requested for a read operation by a first core that are already being accessed (for either reads or previously for writes) by a second core can be marked as shared in the second core, forwarded or intervened to the first core, and also marked as shared in the first core. Both cores then access the shared lines for reads in parallel, without further communication. This protocol can result in multiple cores sharing the same line so that when another core attempts to access (for read shared or exclusive) a line that is already shared by two or more cores, a choice must be made of which core provides the shared copy. A typical cache allocation model would provide the line based on some centralized control heuristic such as, for example, deciding that the core physically closest to the requesting core could provide the line. In some implementations, a specific core's version of the shared line is marked as the shared copy that will be provided for future requests, thereby reducing the time required to access the cache line.
While memory access speed has historically been a key design objective, in today's multiprocessors, power dissipation is an increasingly important design constraint that must be considered, especially when the power dissipation can be different at each core in a multiple heterogeneous core system, or when homogeneous cores not being utilized symmetrically, the power dissipation can be different at each core. In addition, power dissipation (and hence core temperature) can increase when some level of the cache hierarchy (e.g., the L2 cache in a first processing unit) is accessed to intervene shared lines to other cores or to an L2 cache in another processing unit. As will be appreciated, such power dissipation occurs when powering up the control or the sub-arrays of the cache, when reading the line out of the cache, and when forwarding the line across a bus to the requesting core. In some cases, one or more of the cores and their associated cache hierarchies may be dissipating significant power, and it can also be the case that all of the cores are “hot” when they are all dissipating significant power.
While attempts have been made to control the “hot core” problem, such as powering down a “hot” core, such solutions do not provide a mechanism for coherently sourcing a cache line to a requesting core, and otherwise impose an undue limit on the processing capability by powering down the hot core(s). Accordingly, there is a need for a system and method for controlling the effects of power dissipation in a multiprocessor system by efficiently and quickly sourcing cache lines to a requesting core. In addition, there is a need for a multi-core system and method to provide system coherency for cache line requests which takes into account the power consumption status of individual cores. Further limitations and disadvantages of conventional cache sourcing solutions will become apparent to one of skill in the art after reviewing the remainder of the present application with reference to the drawings and detailed description which follow.